Field
Embodiments of the present invention generally relate to methods and apparatus for in-situ cleaning a plasma processing chamber utilized to etch a substrate. Particularly, embodiments of the present invention relate to methods and apparatus for in-situ chamber dry cleaning a plasma processing chamber utilized to etch a metal gate structure formed in semiconductor devices on the substrate.
Description of the Related Art
Ultra-large-scale integrated (ULSI) circuits may include more than one million electronic devices (e.g., transistors) that are formed on a semiconductor substrate, such as a silicon (Si) substrate, and cooperate to perform various functions within the device. Typically, the transistors used in the ULSI circuits are complementary metal-oxide-semiconductor (CMOS) field effect transistors. A CMOS transistor has a gate structure comprising a polysilicon gate electrode and gate dielectric, and is disposed between a source region and drain regions that are formed in the substrate.
Plasma etching is commonly used in the fabrication of transistors and other electronic devices. During plasma etch processes used to form transistor structures, one or more layers of a film stack utilized to form a gate structure (e.g., layers of silicon, polysilicon, titanium nitride (TiN) or titanium oxide (TiO2), hafnium dioxide (HfO2), silicon dioxide (SiO2), metal materials, and the like) are typically exposed to etchants comprising at least one halogen-containing gas, such as hydrogen bromide (HBr), chlorine (Cl2), boron chlorine (BCl3), carbon tetrafluoride (CF4), ethylene (C2H4) and the like, supplied in a processing chamber. For example, as depicted in FIG. 1, a semiconductor device 100 is disposed on a substrate 102. A gate dielectric layer 104, such as SiO2, is disposed on the substrate 102. Subsequently, a high-k material 106, such as a hafnium containing layer, is disposed on the gate dielectric layer 104 followed by a capping layer 108. Suitable examples of the capping layer 108 may be metal layers, such as aluminum metal or lanthanum (La) metal. A metal gate electrode layer 110, such as a TiN or TiO layer, and a poly silicon gate electrode layer 112 is then consecutively formed on the capping layer 108. After etching of the metal gate electrode layer 110, metal containing etching by-products, such as titanium containing residuals or hafnium containing residuals, may be formed during the etching process. The metal containing etching by-products may gradually build up on the surfaces of the substrate 102 as well as chamber components of the processing chamber. The metal containing etch by-products may also attack the surfaces of the chamber components, which in turn detrimentally affects the ability to maintain process control during circuit fabrication. Furthermore, metal containing etching by-products accumulating on components and surfaces of the processing chamber may impact recombination and surface reactions on the chamber walls, thereby affecting the overall substrate etching performance as well as becoming a source of unwanted particles that may contaminate the substrate 102. When the deposited metal containing etch by-products reach a certain thickness, the by-products may peel off from the inner wall of the plasma chamber and contaminate the substrate 102 by falling onto the substrate, causing irreparable defects to the device structure formed on the substrate. Accordingly, it is important to remove and clean such metal containing etching by-products periodically.
Therefore, there is a need for an improved process for cleaning plasma chamber after etching of a substrate.